Video Capture

Video Capture

This page documents the procedure of capturing the video signal of the upper and lower screens of the 3DS.

The information on this page was found by 3DBrew User: Matyapiro31

Pinout_point.jpg

Lower Screen Dump #

Test Points on the front of the board:

#NameTPRED#NameTPGREEN#NameTPBLUE
10CN2-31184R020CN2-39186G024CN1-34188B0
12CN2-32178R119CN2-40180G118CN1-33182B1
13CN2-33172R221CN1-40174G217CN1-32176B2
11CN2-34166R314CN1-39168 (above 180)G323CN1-31170B3
2CN2-35183R422CN1-38185G45CN1-30187B4
3CN2-36177R516CN1-37179G56CN1-29181B5
1CN2-37171R615CN1-36173 (below 179)G67CN1-28175B6
4CN2-38165R79CN1-35167G78CN1-27169B7
#NameTPDescription
25CN2-30189CLK
26CN2-28191VSYNC
27CN2-27190HSYNC

This table (taken from the picture above) shows which TP (test-point) to get the bit of the corresponding color (R=red, G=green, B=blue).

And the TP to get Clock, Vertical-Sync and Horizontal-Sync.

Captured Video Control Signals #

The following picutres show plots of the control signals CLK (TP189), HSYNC (TP190) and VSYNC (TP191). The used sample rate were 50MHz.

The full plot shows about 2.6ms.

Stp_PCLK_VSYNC_HSYNC_full.jpg

This plot shows 1.28us, mainly featuring the clock

Stp_PCLK_VSYNC_HSYNC_0..64.jpg

Setup

The signal capturing was done by using an DE10-NANO FPGA development board, Intel signal tap analyzer and 5 wires soldered to the TPs of an EU-O3DS (roughly 25cm long, parallel wired).

VCD and CVS files: Media: Stp_PCLK_VSYNC_HSYNC.7z (to view the VCD file use GTK Wave or similar programs).